Huawei Unveils 'Tau (τ) Scaling Law': China Defines New Industry Rule for Global Semiconductor Sector for the First Time

On May 25, at the 56th IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, He Tingbo, Board Director and President of Huawei's Semiconductor Business Group, delivered a keynote speech titled "Exploration and Practice of New Semiconductor Pathways," officially introducing to the global industry a new concept named after the Greek letter τ — the "Tau (τ) Scaling Law" . Here, τ represents the "time constant" in circuit theory, denoting the fundamental time required for a signal to transition from one state to another. This is not the launch of a new product, but a new principle guiding the evolution of the semiconductor industry.

For over six decades, the global semiconductor industry has adhered to a single true "constitution" — Moore's Law: roughly every two years, transistors are shrunk to the next generation, relying on geometric scaling to achieve higher integration and performance. However, this path is approaching both physical and economic limits. Below 3nm, the cost of R&D and fab construction for each successive process node rises exponentially. The design budget for a single chip often exceeds one billion US dollars, while the cost per transistor no longer declines. The marginal gains in performance are thinning, and issues such as quantum tunneling, leakage current, and heat dissipation make purely geometric scaling increasingly akin to "dancing on the edge of physical laws." In her peer-reviewed paper, "A Time Scaling Theory for Multi-Layer Electronic Systems," He Tingbo cuts to the heart of the matter: Moore's Law was never about "getting smaller" per se, but about making signals reach their destination faster — the essence being time compression. If that is the case, why not take time itself as the optimization target?

This is the logical starting point of the Tau Scaling Law: replacing "geometric scaling" with "time (τ) scaling." It reduces performance issues spanning twelve orders of magnitude — from transistor switching (picoseconds) to data center task response (seconds) — to a unified metric. The law does not negate Moore's Law; instead, it downgrades geometric scaling to just one of many means of τ reduction, giving packaging, memory bandwidth, and interconnect architecture equal or even greater weight than transistor process nodes.

Under the technical framework, He Tingbo anchors semiconductor evolution to the characteristic time constant τ as a unified metric, decomposing it into a four-layer delay chain spanning devices to systems. On this basis, she proposes a four-tier co-optimization system spanning devices, circuits, chips, and systems, emphasizing that these four layers are not independent local tuning exercises but must form a conductive chain centered on reducing the system-level τ:

Device layer optimizes transistors from materials and structures, pushing down the intrinsic switching delay of the transistor (i.e., the lower bound of device-level τ).
Circuit layer employs "Logic Folding" to break beyond traditional planar layouts, topologically rearranging logic cells in three-dimensional space, "folding" frequently communicating modules together, significantly shortening critical path wiring and reducing RC propagation delay. This enables a leap in chip performance without pursuing extreme physical scaling, instead achieving gains through clever spatial rearrangement.
Chip layer adopts full-stack collaborative design spanning software, architecture, and chip, finely tuning instruction and data flows based on real workloads, increasing parallelism, and reducing end-to-end execution time.
System layer defines a flexible bus (Lingqu Bus) and restructures interconnect protocols, enabling supernode unified memory addressing and native memory semantics, eliminating redundant overhead in end-to-end message passing and synchronization.

Crucially, τ optimization at each layer must propagate to the system layer to deliver tangible value. Thus, process engineers, circuit designers, architects, and system engineers can finally speak a common language — "τ" — something the semiconductor industry has never truly achieved in six decades.

This pathway is not a fantasy. He Tingbo revealed that over the past six years, Huawei has successfully designed and mass-produced 381 chips based on this methodology, covering a wide range of industries. The next-generation Kirin chip, to be released in the autumn of 2026, will be the first commercial product to fully integrate Logic Folding technology. Huawei further projects that by 2031, high-end chips based on the Tau Scaling Law pathway will achieve energy efficiency comparable to the 1.4nm process node. In other words, without relying on the most extreme EUV lithography nodes, it is possible to approach the frontier performance ceiling. In an exclusive interview with Xinhua News Agency, He Tingbo remarked: "Besides physical limits, Huawei — constrained by sanctions — encountered this 'wall' earlier than its peers. 7nm, 5nm, 3nm, 2nm... the numbers keep shrinking and will soon hit the physical limit, and they have also become an overly simplistic metric." She summarized this shift as "returning to the origin and finding another path."

References

1. Xinhua News Agency (Xinhuanet). "Huawei Director Reveals the 'Tau (τ) Scaling Law': No Retreat, Only the Path to Victory." May 27, 2026.

2. He Tingbo. Keynote speech "Exploration and Practice of New Semiconductor Pathways" at ISCAS 2026. May 25, 2026.

3. He Tingbo. "A Time Scaling Theory for Multi-Layer Electronic Systems." ChinaXiv (Chinese Academy of Sciences Preprint Platform), May 25, 2026.